Event Details

Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in AI/ML and many other fields, that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. If time permits, we will outline how to meet those challenges through a broad and organic Industry-Academia Coalition called ÆPeX America – the Advanced Electronics Packaging eXchange for America. We will outline how companies (small and large), research establishments and Universities can join ÆPeX America and benefit and contribute to our progress.

May 9, 2025

Join Zoom Meeting

https://usc.zoom.us/j/97017422125?pwd=Dbrt8MNMrmBV3xalKQJcAiNsggFJjJ.1&from=addon
Meeting ID: 970 1742 2125
Passcode: 937624

Host: Steve Crago
POC: Amy Kasmir

Speaker Bio

Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. In 2023-4, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications.   He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Professor Iyer was also Professor Ramakrishna Rao Visiting Chair Professor at IISc, Bengaluru.