Event Details

The super-exponential rise in the complexity of artificial intelligence (AI) and machine learning (ML) models continues to explode at a rapid pace. For example, in five years, the Large Language Model (LLM) underlying ChatGPT has increased in size by over 10,000 times. Similar explosive growth is occurring in emerging 5G/6G wireless systems. In particular, matrix inversions in the MIMO decoding process have cubic complexity with the number of users that need to be served simultaneously, which also scales the MIMO operations to thousands of antennas per radio tower with hundreds of digital streams. This challenges current front-haul capacity and substantially increases the complexity and costs of radio units (RU). These different dimensions of exponential growth mean that existing computing architectures and integrated system implementations will surely be unable to keep up with the disruptive increases in computational and energy requirements. This presentation will demonstrate the initial research results and ongoing developments of our optical matrix multiplier, RF-over-fiber, and in-package optical-interconnect techniques with advantages of inherent parallelism, high-degree connectivity, and high-speed propagation in silicon-photonics to enable energy- and bandwidth-efficient AI accelerators, wireless channel decoders, front-haul architectures, and panel-scale interposers for super-exponentially growing workloads in AI computing and massive MIMO systems.

August 22, 2025

Join Zoom Meeting
https://usc.zoom.us/j/97017422125?pwd=Dbrt8MNMrmBV3xalKQJcAiNsggFJjJ.1&from=addon
Meeting ID: 970 1742 2125
Passcode: 937624

Host: Steve Crago
POC: Amy Kasmir

Speaker Bio

Tzu-Chien Hsueh (Senior Member, IEEE) received the Ph.D. degree in Electrical and Computer Engineering from the University of California, Los Angeles (UCLA), in 2010. From 2001 to 2006, he was a Mixed-Signal Circuit Design Engineer in Hsinchu, Taiwan. From 2010 to 2018, he was a Research Scientist in Intel Lab Signaling Research and an Analog Engineer in Intel I/O Circuit Technology, Hillsboro, Oregon. Since 2018, he has been an Assistant Professor in Electrical and Computer Engineering at the University of California, San Diego (UCSD). His research interests include wireline electrical/optical transceivers, clock-and-data recovery, data-conversion circuits, on-chip performance measurements/analyzers, and digital/mixed-signal processing techniques. Prof. Hsueh was a recipient of multiple Intel Division and Academy Awards from 2012 to 2018, the 2015 IEEE Journal of Solid-State Circuits (JSSC) Best Paper Award, the 2020 NSF CAREER Award, and the 2022 UCSD Best Teacher Award. He served on the Patent Committee for Intel Intellectual Property (Intel IP) and the Technical Committee for Intel Design & Test Technology Conference (DTTC) from 2016 to 2018. Since 2018, he has served on the Technical Program Committee for IEEE Custom Integrated Circuits Conference (CICC) and as a Guest Associate Editor for IEEE Solid-State Circuits Letters (SSC-L).